• Yorick@piefed.social
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    1 day ago

    May I introduce the VHDL STD library where you can set an output to “don’t care”:

    Wikipedia IEEE-1164

    As an embedded electronics engineer discovering VHDL was a blast and a mindfuck!

    • white_nrdy@programming.dev
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      1 day ago

      Don’t worry, VHDL is still a mindfuck sometimes even after being an FPGA engineer for years (mostly only using VHDL). It’s such a cool language, and I am glad you discovered and are enjoying it!